Mobility Dependence on Crystal Orientation and Strain Engineering

Fig. 1: Process induced strain summary.

This report summarizes the contemporary methods to improve mobility for the Si VLSI technology. A brief introduction for the physics of the strain effect and crystal orientation is presented and the corresponding fabrication methods are summarized. The chief contribution of this report is the summary for the strain effect and mobility dependence on the crystal orientation in Table 3 and Table 4, which can be used for the mobility optimization by using the combination of crystal orientation and the strain-related processes.

As the Si VLSI technology keeps pushing to the dimension limit, a simple scaling scenario "constant electrical field" can no longer give the desired performance. It is mainly due to the increasing electrical coupling under such a small dimension, for example, tunneling could occur and degrade the controllability of the current from the external source. Besides, since the threshold voltage and the sub-threshold slope both are non-scaling factors, as a result, if the Vdd keeps decreasing by following the simple scenario, there is obviously a trade-off lying ahead for the power and speed. There have been proposed many methods to deal with this issue, for example, the I-MOS is one of them which is proposed to solve the sub-threshold slope issue and gives a deeper transition from off to on state. Another way is to boost the current based on the design of new structure and choices of materials. But these may involve the cost and comparability problem with the current technology. Without major change to the current process, strain induced band-structure modification turns out to be the easiest way to increase the mobility and has been the dominant technology now. Besides, electron propagating in different orientation would view different band structure and scattering. So the proper combination of the strain effect (compressive or tensile) on designated substrate and channel orientation is essential in the design of state of the art devices. Finding out the proper combination for best performance is the main focus of this report.

Strain Silicon Theory

It has been known that applying mechanical force could change the resistance of metals because the electron transportation could be retarded due to the deformation of crystal. In the semiconductor, this effect is even more phenomenal since not only the transportation but the electron population related to the band structure also changes. The relationship between stress and electrical resistance is called as piezoresistance, which can be expressed as

where π_i,j is the piezoresistance, σ_i,j is the force (i,j denote the direction for a given coordinate system) and δρ/ρ means the change in resistance.

The physical explanation of piezoresistance-effect actually comes from the change of the band structure. Once the mechanical force is applied, the lattice is distorted, and the lattice symmetry is reduced. This change in real lattice also reflects in the reciprocal lattice, and thus changes the E-k relationship as well. For example, in Si, the 6-fold X-valley degeneracy will split into Δ2, and Δ4. The smaller effective mass Δ2 valley has lower energy and thus accommodates more electrons for transport. The light hole band can also split from the heavy hole band at the zone center, which changes the valence band structure and hole mobility.

This concept is in itself trivial and could be derived; many band diagrams and equations to illustrate this concept can also be found in the literature [3-5] and will not be repeated here. The methodology of this report is to attribute all these physical interpretations into the piezoresistance concept in order to present an easy-to-catch method to clarify the strain and mobility dependence.

It is well known the lattice structure for Si or Ge is diamond structure. If the cubic coordinate system is chosen, the pizeorisitance can be written as a matrix and the relationship can be modeled as follows:

The corresponding metrix elementsvalues for Si and Ge are first measure by Charles Smith in 1954. [1] Since, to first order, mobility is in proportion to the channel conductance, we can conclude that

where the directions L, W and Z depend on the orientation of the device. The piezoresistances for (100) and (110) silicon substrate, the orientations most commonly used, are listed in Tables 1 and 2. [1-2]

L is the channel direction, W is the direction perpendicular to the channel on the surface and Z is the direction perpendicular to both L and Z. It should be noted that a positive value means the resistance increases with tensile stress, so a compressive stress is preferred. Based on this rule, this relation is further simplified into Table 3 indicating either the tensile or compressive strain should be given for mobility improvement.

Here T means tensile is preferred, C means compressive is preferred and - means no significant effect.

Engineering Methods

In practice there are many ways to incorporate the strain into device fabrication. These methods can be categorized into two groups: substrate induced strain (mainly biaxial strain) and process induced strain (mainly uniaxial strain). [3-5] For simplicity we shall focus on the most common configuration, (100) silicon substrate and [110] silicon channel alignment for both PMOS and NMOS. The techniques can easily be modified for different orientations.

- Substrate Strained Silicon (SSS)

To induce the substrate strain a multiple layer structure is usually used, with one relaxed layer between the substrate and the channel. The relaxed layer is usually a graded Si_1-xGe_x layer with increasing x (Ge fraction) from substrate to the channel layer. The channel could be either a Si or Ge layer, which could receive tensile or compressive biaxial strain given the graded buffer layer.

For NMOS, it turns out that in the normal channel alignment ([110] on (100) substrate), biaxial tension splits the conduction band by approximately 6.7 meV per 1% Ge fraction. The sign can also be inferred from Table 3 since tensile strain is preferred in both L and W direction.

However, neither tensile or compressive biaxial strain improves the hole mobility for PMOS very much. There are many reasons for this. First, the valence band split (4 meV per 1% Ge fraction) is not as high as the conduction band, so higher Ge fraction is needed to give decent improvement. Besides, the split also saturates at high Ge fraction. Using such a high Ge fraction in the relaxation layer requires a buffer layer below, which in term complicates the process. Second, the hole mobility improvement actually worsens in the presence of a vertical electrical field (gate bias). The cause is believed to be the decrease of the band separation due to surface potential confinement. Another way to view this effect is from Table 3. We can easily infer that for PMOS, a compressive strain is preferred in the L direction while a tensile strain is preferred in the W direction. So, by simply applying a biaxial strain we cannot satisfy both strain preferences.

From the processing point of view, growing such a multiple layer structure is rather complicated and time consuming. To resolve this problem, a process strain is used to generate uniaxial strain in the desired direction.

- Process Strained Silicon (PSS)

The process-induced strain could be categorized by the placement. The commonly used methods are using SiGe as the S/D for PMOS [6] and SiC as the S/D for the NMOS [10]. The Dual Stress Linear (DSL) technique on top of the poly-silicon gate is also used to create stress. Other currently techniques include the Stress Memorization Technique (SMT) [7], Stress Proximity Technique (SPT) [8] and Shallow Trench Isolation Strain[9].

Since Ge has larger lattice spacing than Si, incorporation of Ge into the Si lattice causes compressive stress on the nearby atoms. So by using SiGe as the source/drain on both sides of the channel, we can apply compressive strain to the channel direction and tensile stress in the perpendicular direction. Both satisfy the strain preference from Table 3. As a result, good improvement of hole mobility is observed. However, since Ge has smaller bandgap, the S/D junction leakage current will increase as a trade-off for the mobility improvement. It's similar to the argument for incorporating SiC as the S/D for NMOS. There C atoms are smaller than than Si atoms, so they shrink the lattice structure when they fit into a Si lattice site. This causes tensile stress on the channel direction. But applying SiC S/D for NMOS is not as effective as SiGe for PMOS. [10]

We could also generate strain vertically by adding a layer on top of the poly gate to stress the channel below. The most commonly used layer is silicon nitride, which also acts as the passivation layer. This nitride layer could be either tensile or compressive depending on the deposition condition. First a highly tensile SiN layer over the entire wafer is deposited by thermal CVD. Then it is patterned and etched from PMOS regions - since PMOS prefers compressive strain. Then a highly compressive SiN layer is deposited by PECVD. Finally, the compressive layer is patterned and etched from NMOS regions. As a result, one single nitride layer with different property can be formed for both NMOS and PMOS. This is called the Dual Stress Liner technique.

Along similar lines, the Stress Memorization Technique (SMT) can be used before the DSL formation. A poly-silicon layer is first amorphorized by implanting Si and then capped by a tensile nitride layer. Then, after recrystallization of the poly-silicon, the reformed poly-silicon gate will "retain" the stress even after the nitride layer is striped away, simply because the lattice has recrystallized under the stress presence. After etching the temporary nitride layer, the dual stress liners as described above could be used.

Another trick to apply the strain is to fill the STI region by using either high density plasma-filled oxide or sub-atmosphere CVD oxide to control the oxide density. This is similar to the S/D technique but with a smaller effect since the distance between STI and channel is farther than S/D and channel. Yet another one, called stress proximity technique, is simply removing the spacer after salicidation on the S/D but before DSL. This allows the subsequent nitride layer to be closer to the channel and thus to propagate stress more effectively to the channel.

To conclude, the theory of strain engineering involving the band structure modification is trivial and could be lumped into the piezoresistance matrix. The engineering methods hence all follow the similar idea: applying the "proper strain" on the designated direction by modifying the device structure. Fig. 1 illustrates and summarizes the process-induced strain. The side effects for strain engineering include the following: (1) The bandgap is smaller, so the leakage current increases. (2) Smaller effective mass implies less density of states (DOS), which decreases the inversion charge density, hence the on-current. Besides, as the device keeps getting smaller, the increase in mobility may not be in proportion to the increase in current. This is because other effects like velocity saturation or ballistic transport may take place. However, the simple strain-related process in increasing the mobility still turns out to be the most popular technique in the current device design technology.

Mobility versus Orientations

In fact, not only does the strain depends on the crystal orientation, the mobility itself also depends on the orientation! Since Si (space group: -4 3m) doesn't have perfect symmetry along all directions, it's intuitive that the electron transport also differs. Table 4 summarizes the relationship of mobility versus orientation. It should be noted that the mobility is actually a function of the applied vertical electrical field and temperature. The peak mobility value is listed here instead of the whole curve in order to make the overview easy to read.

From Tables 3 and 4, it is believed that the (100) and [110] for NMOS combined with (110) and [110] for PMOS orientations are the best combination for getting high mobility in the Si CMOS technology. However, this combination involves different substrate orientations and hence complicates the process.

Although there are other possible methods to improve the device performance, including adoption of different materials and novel structures, silicon strain technology is so superior that it has become widely accepted.

© 2007 Shu-Lu Chen. The author grants permission to copy, distribute and display this work in unaltered form, with attribution to the author, for noncommercial purposes only. All other rights, including commercial rights, are reserved to the author.

References

[1] C. S. Smith, "Piezoresistance Effect in Germanium and Silicon," Phys. Rev. 94, 42 (1954).

[2] Y. Kanda, "Grahical Representation of the Piezoresistance Coefficient in Silicon," IEEE Trans. Elec. Dev. 29, 64 (1982).

[3] J. Welser et. al., "Strain Dependence of the Performance enhancement in strained-Si n-MOSFETs," IEDM Tech. Dig. [Proceedings of the 2003 International Electron Devices Meeting, Washington, D.C.] (IEEE, 2003), p. 373.

[4] K. Rim et. al., "Enhanced Hole Mobilities in Surface-channel Strained-Si p-MOSFETs" IEDM Tec. Dig. [Proceedings of the 1995 International Electron Devices Meeeting, Washington, D.C. ] (IEEE, 1995), p. 517.

[5] J.L. Hoyt et. al.,"Strained silicon MOSFET Technology," IEDM Tech. Dig. [Proc. of the 2002 International Electron Devices Meeting, San Francisico, CA] (IEEE, 2002), p.23.

[6] S. E. Thompson et. al., "A Logic Nanotechnology Featuring Strained-Silicon," IEEE Elec. Dev. Lett. 25, 191 (2004).

[7] C.-H. Chen et. al., "Stress Memorization Technology (SMT) by Selectively Strained-Nitride Capping for Sub-65nm High-Performance Strained-Si Device Application," VLSI Dig. Tech. Papers [Proceedings of the IEEE Symposium on VLSI, Honolulu] (IEEE, 2004), p. 56.

[8] X. Chen et. al., "Stress Proximity Technique for Performance Improvement with Dual stress Liner at 45 nm Technology and Beyond," VLSI Dig. Tech. Papers [Proceedings of the IEEE Symposium on VLSI Test, Berkeley] (IEEE, 2006), p. 60.

[9] C. Le Cam et. al., "Low Cost Drive Current Enhancement Technique Using Shallow Trench Isolation induced Stress for 45-nm node," ibid., p. 82.

[10] K.W. Ang et. al., "50nm Silicon-On-insulator N-MOSFET Featuring Multiple Stressors: Silicon-Carbon Source/Drain Region and Tensile Stress Silicon Nitride Liner," ibid., p. 66.